Behaviour

input A6   1.0 V → 6 % duty   5.0 V → 92 % duty   linear, clamped      output D3 500.000 Hz (Timer2 hardware, 250 counts = 0.4 % steps)
dead input  < 0.5 V for 100 ms → FAULT: output 6 %   (back to RUN after > 0.7 V for 100 ms)   also: ADC failure, boot (until 100 ms of valid input), stalled main loop
filter      32-sample average, low-pass 1/8 per 10 ms (90 % of a step in ~180 ms), 1.0-count hysteresis with snap zones at both ends (no duty jitter, 6.0 % and 92.0 % always reachable)

Stability features

PWM is generated by hardware and keeps running if the code stalls · software watchdog (100 Hz interrupt) forces 6 % after 100 ms without main-loop progress · the Timer2 configuration is verified and repaired every 10 ms (regfix counts repairs) · serial output is queued and never blocks control · no hardware watchdog (old Nano bootloaders can reset-loop with one) · boot counter in EEPROM: a count that grows without you resetting the board means unexpected resets.

Wiring

Put a 10–100 kΩ pull-down from A6 to GND so an open wire reads 0 V (a floating A6 cannot be detected). Never exceed Vcc + 0.5 V on A6. The input scale assumes Vcc = 5.000 V: on USB (≈ 4.7 V) readings are high by the same ratio, and inputs above Vcc read as full scale. Power through VIN (7–12 V) for a true 5 V rail. Pull D3 to GND with a resistor if the load needs a defined level while the board boots (about 1–2 s, the pin floats).

Telemetry line

T ms= adc= mv= fmv= st=RUN|FAULT why=NONE|INIT|LOW|ADC clamp=-|LO|HI k= duty=(permille) inj= loop=(max gap, µs) stall= regfix= adcerr= txdrop= vcc=(mV, bandgap ±10 %)
I fw= hz= kmin= kmax= n= in= faultin= faultout= vref= boots= rst=(MCUSR: 1 power-on, 2 external, 4 brown-out, 8 watchdog) test=       REG TCCR2A= TCCR2B= OCR2A= OCR2B= …